Basics of synthesis & Timing Constraints

Aimtron Foundation ( is organizing a series of Webinars, delivered by Industry Experts.

The Aim of this workshop is to guide and help students to understand industry’s need and what industry is looking from engineering students. This will help you to focus on domains that interests you.

They say you are what you eat. The same analogy for VLSI design is quality of the design is quality of the constraints. Timing constraints play a very important role because it sets the tone for every stage of the design flow. When somebody refers to design complexity it is not just design size but also constraints the designer is dealing with. Reviewing constraints and making sure it meets design intent is very important. Better timing constraints lead to better timing closure.

During the session we will cover key timing constraints, impact of these constraints on the design flow, how to fix the constraints issue  and also how it helps timing closure.

About Pradeep C R :
Pradeep holds a Master’s degree in VLSI System Design from Coventry University UK and a bachelor’s degree in Electronics and Communications Engineering from BITM, VTU.

Pradeep has 15+ years experience in the Semiconductor industry. Currently he is working for Ausdia Inc, as a Director Technical Account Management for Asia Pac Region.

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