Webinar topic:

“Flip Chip and Advanced Packaging Technologies” As scaling of transistors slows down, advanced semiconductor packaging is becoming crucial for enabling miniaturization while driving higher performance, optimized heat dissipation, and enhanced connectivity in electronic devices.

As the demand for more powerful and portable electronic devices continues to grow, advanced packaging techniques such as wafer level packaging and 2.5D/3D packaging are becoming increasingly important.

During this webinar, Dr. Raghu Chaware will present an overview of packaging technology and its evolution over time. He will discuss high level assembly process steps and key factors that influence yield, quality and reliability of flip chip packages. His talk will also cover drivers behind recent advancements in flip packaging technologies and new developments taking place in 2.5D and 3D packaging methods that are driving significant performance gains in GPUs, CPUs, FPGAs and other application specific processing units. 

About Dr. Raghu Chaware :

Raghu has more than 20 years of experience in developing advanced packaging technology for logic devices with expertise in Design for Manufacturing, reliability engineering, statistical methods, and yield optimization.

He is an Inventor and co-inventor of multiple patents (>20 patents) on industry-leading flip chip and 2.5/3D interconnect packaging technology. During his tenure at Xilinx, he led the manufacturing ramp team that introduced the 1st ever production quality 2.5D FPGA package.

He has a Ph.D. in Systems Science and Industrial Engineering from State University of New York at Binghamton (Binghamton University) and a master’s degree in Material Science from University of Mississippi. Currently, he is a Fellow at Lattice Semiconductor and leads advanced assembly/packaging development and production teams.