3. Basics of synthesis & Timing Constraints

Topic:  Timing Constraints and Timing Closure 
They say you are what you eat .The same analogy for VLSI design is quality of the design is quality of the constraints. Timing constraints play a very important role because it sets the tone for every stage of the design flow. When somebody refers to design complexity it is not just design size but also constraints the designer is dealing with. Reviewing constraints and making sure it meets design intent is very important.  Better timing constraints lead to better timing closure .
During the session we will cover key timing constraints , impact of these constraints on the design flow, how to fix the constraints issue  and also how it helps timing closure.
About Pradeep C R :
Pradeep holds a Master’s degree in VLSI System Design from Coventry University UK and a bachelor’s degree in Electronics and Communications Engineering from BITM , VTU .

Pradeep has 15+ years experience in the Semiconductor industry . Currently he is working for Ausdia Inc , as a Director Technical Account Management for Asia Pac Region . Prior to Ausdia , Pradeep was a staff applications consultant for Synopsys Design Methodology Solution (DMS) Products, chip-level static timing analysis (STA) lead at Microchip (Formerly PMC Sierra), lead application engineer at Extreme DA supporting GoldTime, field applications team supporting Mentor Graphics AMS suite (CoreEL Technologies) and Field Applications team supporting ASM assembly and fabrication product line

Pradeep worked on various aspects of VLSI design , fabrication and manufacturing flow like wafer processing / Fab related , chip assembly / manufacturing , design implementation , physical design , Analog and Mixed signal design flow, Physical verification , RC Extraction and Static Timing Analysis (STA) . For the past few years he is focused in the timing sign off and timing constraints domain .
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